This application is based upon and claims priority of Japanese Patent Application No. 2002-078419, filed on Mar. 20, 2002, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device suitable for manufacturing a flash memory and a logic circuit or the like having the flash memory on board.
2. Description of the Related Art
In a nonvolatile memory such as a flash memory, as shown in FIG. 13, a memory cell array region 101 in which floating-gate type memory cells 103 are arranged in a matrix form and a peripheral transistor region 102 including a logic circuit (not shown) formed on the periphery of the memory cell array region 101 for controlling the operation of the memory cells 103 and the like are provided. In each of the memory cells 103, a control gate CG, a floating gate FG, a source diffusion layer S, and a drain diffusion layer D are provided. The control gate CG is shared by a plurality of memory cells 103 arranged in a direction in which the control gate CG itself extends. Similarly, the source diffusion layer S is shared by the plurality of memory cells 103 arranged in the direction in which the control gate CG extends. The source diffusion layer S is also shared by a plurality of memory cells 103 arranged perpendicularly to the direction in which the control gate CG extends. The drain diffusion layer D of each of the memory cells 103 is connected to the same bit line (not shown). In the logic circuit, a plurality of MOS transistors 104 and capacitors (not shown) and the like are formed. The MOS transistor 104 is provided with a source/drain diffusion layer SD and a gate electrode G.
Such a nonvolatile memory is manufactured by the following method. FIGS. 14A and 14B to FIGS. 32A and 32B are sectional views showing a conventional method of manufacturing a nonvolatile memory in the order of process steps. Incidentally, FIG. 14A to FIG. 32A are sectional views taken along the line Ixe2x80x94I in FIG. 13, and FIG. 14B to FIG. 32B are sectional views taken along the line IIxe2x80x94II in FIG. 13.
First, as shown in FIG. 14A and FIG. 14B, an element isolation insulating film 2a which defines the memory cell array region 101 and the peripheral transistor region 102, and element isolation insulating films 2b which define the memory cells 103 are formed in the surface of a semiconductor substrate 1 such as a P+ silicon substrate. The element isolation insulating films 2a and 2b can be formed, for example, by an STI (Shallow trench isolation) or LOCOS (Local oxidation of silicon) method.
Then, as shown in FIG. 15A and FIG. 15B, an N-well 1a is formed on the surface of the semiconductor substrate 1 in the peripheral transistor region 102, and thereafter a tunnel oxide film 3 is formed on the surface of the semiconductor substrate 1 in each of element forming regions.
Subsequently, as shown in FIG. 16A and FIG. 16B, a polycrystalline silicon film 4 is formed on the entire surface. A resist film 5 is formed on the polycrystalline silicon film 4, and openings 5a are formed in regions of the resist film 5 which match with the element isolating films 2b by photolithography technology. The polycrystalline silicon film 4 is patterned by etching the polycrystalline silicon film 4 with the resist film 5 as a mask.
Thereafter, as shown in FIG. 17A and FIG. 17B, the resist film 5 is removed, and an insulating film 6 is formed on the entire surface.
Subsequently, as shown in FIG. 18A and FIG. 18B, a resist film 7 which allows the peripheral transistor region 102 to be exposed is formed.
As shown in FIG. 19A and FIG. 19B, the insulating film 6, the polycrystalline silicon film 4, and the tunnel insulating film 3 in the peripheral transistor region 102 are removed by etching with the resist film 7 as a mask.
As shown in FIG. 20A and FIG. 20B, the resist film 7 is removed, and a gate insulating film 8 is formed on the surface of the well 1a in the element forming region of the peripheral transistor region 102. Moreover, a polycrystalline silicon film 9 and a silicon nitride film 10 as an antireflection film are formed in sequence on the entire surface.
Thereafter, as shown in FIG. 21A and FIG. 21B, a resist film 11 for covering each of regions where the control gate electrodes of the memory cells 103 are formed and each of regions where the gate electrodes of the MOS transistors 104 are formed is formed on the silicon nitride film 10.
Subsequently, as shown in FIG. 22A and FIG. 22B, the silicon nitride film 10 and the polycrystalline film 9 are removed with the resist film 11 as a mask.
As shown in FIG. 23A and FIG. 23B, the resist film 11 is removed, and a resist film 12 which allows the memory cell array region 101 to be exposed is formed.
As shown in FIG. 24A and FIG. 24B, the insulating film 6 and the polycrystalline film 4 are removed with the resist film 12 and the silicon nitride film 10 as the antireflection films as masks.
Thereafter, as shown in FIG. 25A and FIG. 25B, arsenic is doped as an N-type impurity into the surface of the semiconductor substrate 1 in a self-alignment manner by an impurity doping technique, so that a source diffusion layer 13S and a drain diffusion layer D are formed. Furthermore, the resist film 12 is removed, and phosphorous is doped into only the source diffusion layer 13S by the impurity doping technique with a resist film (not shown) in which an opening is formed only in a region matching with the source diffusion layer 13S as a mask.
Subsequently, as shown in FIG. 26A and FIG. 26B, the resist film 12 is removed, and a resist film 14 which allows the peripheral transistor region 102 to be exposed is formed. A low-concentration diffusion layer 15 is then formed by doping a P-type impurity into the surface of the well 1a in the self-alignment manner by means of the impurity doping technique.
As shown in FIG. 27A and FIG. 27B, the resist film 14 is removed, and a silicon oxide film (not shown) is formed on the entire surface, for example, by a chemical vapor deposition (CVD) method. By subjecting this silicon oxide film to anisotropic etching, a sidewall insulating film (sidewall spacer) 16 is formed on each side of the silicon nitride film 10, the polycrystalline silicon film 9, the insulating film 6, and the polycrystalline silicon film 4 in the memory cell array region 101 and the silicon nitride film 10 and the polycrystalline silicon film 9 in the peripheral transistor region 102.
Subsequently, as shown in FIG. 28A and FIG. 28B, a silicon oxide film 17 is formed on the surface of each of the source diffusion layer 13S, the drain diffusion layer 13D, and the low concentration diffusion layer 15 by surface oxidation. On this occasion, the thickness of the silicon oxide film 17 formed on the surface of the source diffusion layer 13S, into which the higher-concentration impurity is doped, is largest due to oxidation enhanced diffusion (enhanced oxidation).
Thereafter, as shown in FIG. 29A and FIG. 29B, the silicon nitride film 10 is removed by wet processing. On this occasion, the silicon oxide film 17 is formed on the surface of each of the source diffusion layer 13S, the drain diffusion layer 13D, and the low-concentration diffusion layer 15, and hence these diffusion layers are not damaged.
Subsequently, as shown in FIG. 30A and FIG. 30B, after a resist film 18 which allows the peripheral transistor region 102 to be exposed is formed, a high-concentration diffusion layer 19 is formed by doping a p-type impurity with a higher concentration than when the low-concentration diffusion layer 15 is formed into the surface of the semiconductor substrate 1 in the self-alignment manner by the impurity doping technique. A source/drain diffusion layer 20 with an LDD structure is composed of the low-concentration diffusion layer 15 and the high-concentration diffusion layer 19.
Thereafter, as shown in FIG. 31A and FIG. 31B, the resist film 18 is removed, the silicon oxide film 17 is removed by the wet processing, and a stacked film (not shown) composed of a Co film and a TiN film is formed on the entire surface. The stacked film and each of the source diffusion layer 13S, the drain diffusion layer 13D, the source/drain diffusion layer 20, and the polycrystalline silicon film 9 are reacted with each other by RTA (Rapid thermal Annealing) to form a metal reaction layer (CoSi layer) 21. Moreover, after the unreacted stacked film is removed, RTA is performed so that the resistance of the metal reaction layer 21 is lowered. In other words, the metal layer 21 with a low resistance value is formed by a salicide process.
Subsequently, as shown in FIG. 32A and FIG. 32B, a bulk interlayer insulating film 22 is formed on the entire surface. Thereafter, the formation of contact holes in the interlayer insulation film 22, the formation of wires, and so on are performed by a well-known method, and thus the nonvolatile memory is completed.
In the aforementioned conventional manufacturing method, however, as described above, the thickness of the silicon oxide film 17 is largest in its portion which is formed on the surface of the source diffusion layer 13S due to enhanced oxidation. The silicon oxide film 17 is removed by the wet processing for removing the silicon nitride film 10 and by the wet processing before the salicide process, but there is a problem that the silicon oxide film 17 formed on the surface of the source diffusion layer 13S is not fully removed because it is thick. If the silicon oxide film 17 remains on the source diffusion layer 13S, this hinders the formation of the CoSi layer 21. Therefore, the wet processing before the salicide process is performed sufficiently. However, when the time of the wet processing is lengthened, a bird""s beak recedes in case that the element isolation insulating films 2a and 2b are formed by LOCOS, and in case that they are formed by STI, the promotion of an STI divot (Oxide Recess) is accelerated so that junction leakage at an end portion of an active region is increased. Moreover, there is a possibility that the sidewall oxide film 16 recedes so that desired reliability and element characteristic (especially, retention characteristic of the nonvolatile memory and the like) is not obtained. Such a situation is marked in the nonvolatile memory.
The present invention is made in view of the aforementioned problem, and its object is to provide a method of manufacturing a semiconductor device capable of easily removing an oxide film formed by enhanced oxidation in a memory cell array region even if an oxide film with a sufficient thickness is formed as a protective film on the surface of a diffusion layer of a peripheral transistor region.
The present inventor attained to aspects of the invention shown below as a result of earnest examination.
A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device comprising a memory cell array region and a peripheral transistor region provided on the periphery of the memory cell array region. This method of manufacturing the semiconductor device is characterized by comprising the steps of: forming a diffusion layer provided in each of memory cells in the memory cell array region and a diffusion layer provided in the peripheral transistor region on the surface of a semiconductor substrate; forming a silicon oxide film on the surface of each of the diffusion layers by oxidation treatment; and thickening the silicon oxide film only in the peripheral transistor region by subsequent oxidation treatment.
In the present invention, after the silicon oxide film is formed on the surface of each of the diffusion layers, the silicon oxide film only in the peripheral transistor region is thickened, whereby the silicon oxide film in the memory cell array region can avoid being thickened more than necessary. Accordingly, defects such as recession of a bird""s beak, an increase in junction leakage, and recession of a sidewall oxide film which conventionally occur when the silicon oxide films in the memory cell array region and the peripheral transistor region are removed, that is, when the wet processing is performed before a salicide process can be prevented.